Interleaved Convolutional Code and Its Viterbi Decoder Architecture
نویسندگان
چکیده
منابع مشابه
Interleaved Convolutional Code and Its Viterbi Decoder Architecture
We propose an area-efficient high-speed interleaved Viterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code. The state-parallel architecture uses as many add-compare-select (ACS) units as the number of trellis states. By replacing each delay (or storage) element in state metrics memory (or p...
متن کاملFPGA Implementation of Convolutional Encoder And Hard Decision Viterbi Decoder
In this paper, we concern with designing and implementing a convolutional encoder and Viterbi decoder which are the essential block in digital communication systems using FPGA technology. Convolutional coding is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a...
متن کاملConstraint Length Parametrizable Viterbi Decoder for Convolutional Codes
Convolutional codes are the widely used as Forward Error Correction (FEC) codes that are used in robust digital communication system. The parameterized implementation of a Viterbi decoder is presented in this paper where we can fix the constraint length for a code rate of 1 2 . This improves the decoding performance in area, accuracy and computational time. Viterbi algorithm is the widely emplo...
متن کاملImplementation of Viterbi Decoder with Variable Code Rate
It is well known that data transmissions over wireless channels are affected by attenuation, distortion, interference and noise, which affect the receiver’s ability to receive correct information. Convolution encoding with VITERBI decoding is a good forward error correction technique suitable for channels affected by noise degradation. It has been widely deployed in many wireless communication ...
متن کاملA new Viterbi decoder design for code rate k/n
A novel VLSI architecture is proposed for implementing a long constraint length Viterbi Decoder (VD) for code rate k=n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. At each level, the...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: EURASIP Journal on Advances in Signal Processing
سال: 2003
ISSN: 1687-6180
DOI: 10.1155/s1110865703309126